Bench build for a standalone ATmega328P-PU that reads the Stern trough opto board
(520-7001-00A) over its VCC/RCK/SCK/MISO/GND
connector and re-presents the 7 opto channels as clean switch signals for OPP —
replacing the fragile hand-soldered per-leg taps that caused the wiring damage
logged in commit 859a6b9.
Do this on every chip pulled from stock — don't assume factory-default fuses. A truly fresh chip defaults to its internal oscillator anyway, but these are inventory spares of unknown history: if one was previously configured for an external crystal, it will sit dead with no clock signal and no error message, silently waiting for a crystal that isn't there. Burning the fuses explicitly avoids that failure mode regardless of a chip's past.
ArduinoISP sketch onto it."ATmega328 on a breadboard (8 MHz internal clock)", with the ISP shield as programmer. ATmega328P-PU (DIP-28)
┌───────\/───────┐
RESET ●────1─┤PC6 PC5├─28 (unused)
(unused) ●────2─┤PD0(RXD) PC4(SDA)├─27 (unused)
(unused) ●────3─┤PD1(TXD) PC3├─26 (unused)
(unused) ●────4─┤PD2 PC2├─25 (unused)
mirror → PD3────5─┤PD3 PC1├─24──→ mirror: s-trough-jam
mirror → PD4────6─┤PD4 PC0├─23──→ mirror: s-trough6
+5V ●────7─┤VCC GND├─22──● GND
GND ●────8─┤GND AREF├─21──● GND (via 0.1µF, optional)
(no xtal) ●────9─┤PB6(XTAL1) AVCC├─20──● +5V
(no xtal) ●───10─┤PB7(XTAL2) PB5├─19──→ Stern SCK
mirror → PD5───11─┤PD5(mirror) PB4├─18──→ Stern MISO
mirror → PD6───12─┤PD6(mirror) PB3├─17 (unused, MOSI)
mirror → PD7───13─┤PD7(mirror) PB2├─16──● +5V (forces SPI master)
RCK → PB0───14─┤PB0(RCK) PB1├─15 (unused)
└────────────────┘
| Pin(s) | Signal | Connect to |
|---|---|---|
| 7, 20 | VCC, AVCC | +5V rail |
| 8, 22 | GND ×2 | GND rail |
| 1 | RESET | +5V through 10 kΩ |
| 7–8 | — | 0.1 µF cap, right at the chip |
| 21 | AREF | 0.1 µF cap to GND (optional) |
| 9, 10 | XTAL1/2 | leave floating — internal oscillator |
| 16 | SS (PB2) | +5V — forces SPI master mode |
| 17 | MOSI (PB3) | leave floating — unused |
| Stern pin | ATmega328P pin | Notes |
|---|---|---|
GND | GND rail | shared ground |
VCC | +5V rail | verify opto board current draw before backfeeding it |
SCK | pin 19 (PB5) | hardware SPI clock |
MISO | pin 18 (PB4) | hardware SPI data in |
RCK | pin 14 (PB0) | plain GPIO, toggled by firmware to latch |
Build a proper mating connector for the board's existing header — no new solder joints on the Stern board itself.
Bench: each through a resistor + LED to GND. Final install: same 7 pins go straight to OPP's existing switch-wing positions.
| Pin | Mirrors | Bench test |
|---|---|---|
| 5 (PD3) | s-trough1 | resistor → LED → GND |
| 6 (PD4) | s-trough2 | resistor → LED → GND |
| 11 (PD5) | s-trough3 | resistor → LED → GND |
| 12 (PD6) | s-trough4 | resistor → LED → GND |
| 13 (PD7) | s-trough5 | resistor → LED → GND |
| 23 (PC0) | s-trough6 | resistor → LED → GND |
| 24 (PC1) | s-trough-jam | resistor → LED → GND |
SS, MOSI, SCK as outputs per Section 2).RCK low. To read a frame: pulse RCK high→low to latch the 8 parallel opto bits. The board inverts RCK (through its 74HC540) before the shift register's SH/LD, so this is the reverse of a bare 74HC165.0x00 to SPDR, wait for SPIF) — result in SPDR has one bit per channel, MSB first. On a 520-8516-00: bit 7 = unused (always 0), bit 6 = jam, bits 5→0 = trough positions 1→6; 1 = clear, 0 = blocked.BIT_INVERT true on all channels): an output goes high when its opto is blocked. With the MPF switches set to type: NC, each reads active when a ball is there and s-trough-jam active when jammed — confirmed working on the cabinet 2026-10-04.